CPUs That Require More Than One Voltage
Newer CPUs will require more than one voltage. Even though all CPUs from AMD have an integrated memory controller, only socket AM3 CPUs require a separated voltage for this circuit. So on socket AM3 motherboards the voltage regulator circuit will generate two separated voltages for the CPU, one for the “main” part of the CPU (“Vcore”) and another for the integrated memory controller. That is why we knew, in Figure 15, that the extra phase was for feeding the CPU integrated memory controller: because that was a socket AM3 board.
With Intel CPUs, only socket LGA1156 and socket LGA1366 CPUs have an integrated memory controller. So on these motherboards the voltage regulator circuit will generate two voltages, one for the “main” part of the CPU (“Vcore”) and another for the integrated memory controller (“VTT”). On socket LGA1156 motherboards supporting CPUs with integrated video controller (e.g., the ones based on H55 and H57 chipsets) the voltage regulator circuit will generate a third voltage for the CPU, to be used by the integrated video controller (“VAXG”).
On motherboards where the voltage regulator circuit provides more than one voltage to the CPU, the manufacturer will refer to it like “x+y” or “x+y+z”, where “x” is the number of phases for the CPU main voltage (“Vcore”), “y” is the number of phases for the CPU integrated memory controller and “z” is the number of phases for the CPU integrated video controller. The motherboard shown on Figures 14 and 15 had a “3+1” configuration, for example.
Below we summarize what kind of motherboard feeds the CPU socket with more than one voltage.
|Socket||Voltages for the CPU|
|754, 939, 940, AM2, AM2+, 775 and older||One|
|AM3, 1156, 1366||Two|
|1156 with H55, H57 and Q57 chipsets||Three|
Although in this tutorial we focused on the voltages required by the CPU, all motherboards will have at least one phase for feeding the memories and one phase for feeding the chipset. If you look around you will be able to spot these phases (see Figure 18), unless when the memory phase is placed close to the CPU phases, like it happened on the example from Figure 12.