IDF Spring 2006 Coverage

[nextpage title=”Introduction”]

Intel Developer Forum (IDF) Spring 2006 edition has just started in San Francisco, CA. Today several announcements were made, the most important one being the details of Intel’s next-generation microarchitecture, now called Core, which will be used on Intel’s forthcoming processors. In this article you will see the highlights of the opening keynote given by Justin Rattner, Intel’s CTO, with the latest announcements by Intel on the CPU arena.

Rattner talked about his concern with power consumption and presented a very interesting chart showing energy per instruction vs. performance of several Intel CPUs, i.e., how much energy a given instruction consumes to be processed and the driven performance. As you can see on the chart, in Figure 1, this ratio was increasing rapidly until Pentium 4, but dropped to the same level of the very first Pentium processor with Pentium M. That is why Pentium M was the architecture of choice when Intel decided to replace Netburst architecture (which is used by Pentium 4). This ratio got even better with the introduction of Duo Core CPU (a.k.a. Yonah).

Figure 1: Energy per instruction vs. performance.

Intel’s CTO also bragged about being one year ahead of competition in delivering 65 nm CPUs in volume to the market and showed us some interesting figures. Intel’s 65-nm process provides 20% greater performance and consumes 30% less energy than Intel’s 90-nm process. Intel’s 45-nm process will reach the market next year and will provide 20% performance increase and a 30% power reduction compared to 65 nm process.

Figure 2: Intel’s 65-nm process advantages over 90-nm process.

Figure 3: Intel’s 45-nm process advantages over 65-nm process.

With that, Ratter introduced Intel’s new microarchitecture, Core.

[nextpage title=”Core Microarchitecture”]

Core microarchitecture is based on Pentium M’s, which in turn is based on Pentium III’s. For a better understanding on this subject, we recommend you to read our tutorial Inside Pentium M Architecture.

Figure 4: Intel Core microarchitecture.

This new architecture introduces the following new features over Pentium M’s:

• 14-stage pipeline (Intel has never turned public Pentium M’s pipeline; Pentium III used a 11-stage one).
• Micro-fusion: concept introduced on Pentium M, where the instruction decoder fuses two micro-ops into one micro-op in order to save energy and improve performance.
• Macro-fusion: new feature, the CPU fuses two macro-ops (x86 instructions) into just one instruction to be sent to the instruction decoder. The idea is to save energy and improve performance.
• Single-cycle 128-bit SSE.
• Shared L2 memory cache: instead of each CPU core having an individual memory cache, the CPU cache is shared between the cores. This helps preventing that the CPU runs out of cache, situation where it has to the slow RAM memory to grab more instructions and data.
• Advanced pre-fetch.
• Memory disambiguation.
• Advanced power gating.

Due to the keynote dynamics Rattner wasn’t able to explain in depth details about each one of these features. However we are scheduled to attend to a class specifically about the new Core microarchitecture, and as soon as we have this information we will publish a tutorial explaining in details this new microarchitecture.

Rattner also gave an idea how CPUs based on this new microarchitecture will perform compared to CPUs from current-generation CPUs. Merom will be 20% faster than a comparable Core Duo T2600 and keeping the same power consumption; Conroe will be 40% faster and consume 40% less energy than a comparable Pentium D (950 model); and Woodcrest will be 80% faster and consume 35% less energy than a comparable Xeon (2.8 GHz, dual-core, 2 MB L2 cache). Nowadays on a Xeon-based server the CPU represents almost 50% of the system consumption. With Woodcrest, the CPU consumption represents only 33%, and thus the other parts of the server should be optimized to consume less power in the near future.

By the way, Conroe’s TDP (Thermal Power Design) will be of 65 W.

[nextpage title=”More On Multi-Core”]

Another important announcement on this morning keynote was the confirmation that Intel will deliver quad-core CPUs next year. With that, Rattner decided to explain why multi-core technology is better than just raising the CPU clock.

The chart in Figure 5 is quite interesting. If you overclock your CPU by 20%, the performance won’t increase 20% (since the overall performance of a computer doesn’t depend only on the CPU) and power consumption will increase a lot (73%). However, if you underclock your CPU by 20%, the power consumption will drop a lot (50%), while the performance won’t drop that much (87% of the original performance).

Figure 5: Overclocking and underclocking effects on performance and power.

So, if you get two “underclocked” CPUs and build them dual-core, the power consumption will be equivalent of a single-core CPU running at its full clock rate, however the performance leap will be impressive (73% greater, according to Intel), achieving the same performance level of an overclocked CPU but consuming far less.

Figure 6: The dual-core approach.