Atom is a low-power CPU from Intel with very low power dissipation (less than 3 W), targeted to laptops or handheld devices with internet access – dubbed MIDs, Mobile Internet Devices. In this tutorial we will explore the architecture used on this CPU.
It is important to know that there are two flavors of Atom CPUs. Atom series 2xx and N2xx (at this publishing only 230 and N270 models were available) – codenamed “Diamondville” – are targeted to laptops (because they use chipsets from Intel 945 series, which are big and use two chips) while Atom series Z5xx – codenamed “Silverthorne” – are targeted to handheld devices with internet access, not only because they use a new chipset called US15W, which is very small and uses only one chip, but also because Atom Z5xx are physically smaller than other Atom CPUs (14 x 13 mm against 22 x 22 mm).
You may also hear references to the Centrino Atom plataform (codenamed “Menlow”). This platform consists of an Atom CPU, the new US15W chipset (codenamed “Poulsbo”) and radio capability (WiFi, Bluetooth, etc).
Speaking of codenames, we also have “Moorestown,” which will be the next version of Centrino Atom, scheduled to reach the market in 2009 or 2010 and will feature a “Lincroft” Atom CPU, a “Langwell” chipset and an “Evans Peak” radio chip.
The main specs from Atom CPU include:
- Full compatible with x86 instruction set, meaning it can run directly PC software and operating systems. Several other CPUs targeted to handheld devices have proprietary instruction set.
- Very low Thermal Design Power (TDP): 4 W for the 230 model, 2.5 W for the N270 and between 2 W and 2.64 W for the Z5xx models.
- Hyper-Threading technology.
- Virtualization technology.
- Execute disable bit (NX bit).
- SSE3 instruction set.
- 400 MHz or 533 MHz external clock (100 MHz or 133 MHz transferring four data per clock cycle).
- 128-bit internal datapath (“Digital Media Boost”).
- Enhanced Speed Step (except on Atom 2xx models).
- 32 KB L1 instruction cache and 24 KB L1 data cache
- 512 KB L2 cache
- Dynamic cache sizing: ability to turn off portions of the memory cache when CPU enters C4 or C4E power-saving modes (not available on Atom 2xx models).
- 16-stage pipeline
- Manufactured under 45-nm process
- Can be paired with a mobile Intel 945-class chipset (Atom 2xx and Nxxx models) or with an Intel US15W (“Poulsbo”) chipset (Atom Z5xx models). Models 2xx and Nxxx are targeted to laptops, while Z5xx models are targeted to handhelds with internet capability.
- 437 pins (“Diamondville” models, i.e., 2xx and Nxxx) or 441 pins (“Silverthorne” models, i.e., Z5xx).
Now let’s see in more details the main features found on Atom processor.
Atom is based on a entire new microarchitecture, having the same instruction-set of CPUs based on Core microarchitecture, like Core 2 Duo. The main difference of the microarchitecture used on Atom is that it processes instructions in order, which is the way CPUs up to the first Pentium used to work. CPUs starting with Pentium Pro and Pentium II use an out-of-order engine. This change was made in order to save energy, since the components in charge of issuing and controlling microinstructions execution could be removed. Atom can decode two instructions per clock cycle.
Pipeline is a list of stages that each instruction must go through in order to be fully executed. For more explanation, read our tutorial called How a CPU Works.
Atom has a 16-stage pipeline, which is a little bit longer than current Core 2 CPUs. This was done for some reasons. First, this allows a better power efficiency. More stages means more units, which can be spread across the chip and thus better spreading heat production, instead of having fewer units which would concentrate heat on a single point. With more units the probability of having some of them idle is higher compared to a CPU with fewer units, meaning that they can be turned off for power savings. Another advantage in a longer pipeline is that the microarchitecture can achieve higher clock rates. The reason why is that each unit will have fewer transistors, making it easier to pump clock rate.
Another feature found on Atom is a true 128-bit internal datapath, feature introduced with processors based on Core microarchitecture (e.g., Core 2 Duo). On previous CPUs the internal datapath was of 64 bits only. This was a problem for SSE instructions, since SSE registers, called XMM, are 128-bit long. So, when executing an instruction that manipulated a 128-bit data, this operation had to be broke down into two 64-bit operations. The 128-bit internal datapath makes Atom faster to process SSE instructions that manipulate 128-bit data. Intel calls this feature “Digital Media Boost.”
As mentioned, Atom CPUs have a 32 KB L1 instruction cache, a 24 KB L1 data cache and a 512 KB L2 cache. They don’t have an integrated memory controller, memory types and maximum sizes are defined by the memory controller inside the chipset, not by the CPU.
Atom also features Hyper-Threading technology, which is the ability of using unused CPU units to form a second virtual CPU, making the operating system to see each CPU core as having two CPUs (two threads, on the industry’s jargon) even though only one core is physically present. Of course this technique is less efficient than having two real CPU cores, but this extra core – and thus extra performance – you are gaining for free.
[nextpage title=”Power-Saving Modes”]
Not all Atom CPUs are equal, and the most important difference between them is on the supported power-saving modes. For a detailed explanation of all power-saving modes, please read or Everything You Need to Know About the CPU C-States Power Saving Modes tutorial.
Atom 2xx (at this writing only Atom 230 was available) supports only C1 (Halt) power-saving mode, introducing a new C1 sub-mode, called MWAIT, which is entered upon the execution of an instructional called “MWAIT,” thus being similar to the traditional C1 mode, which is entered upon the execution of the “HALT” instruction. The difference, however, is that on regular Halt state the CPU can only exit when an interruption is given, while on the MWAIT state other events can put the CPU back on fully operational state.
Atom Nxxx (at this writing only Atom N270 was available) supports modes C1, C1E, C2, C2E, C3, C4 and C4E.
And Atom Z5xx supports all above plus C6 mode.
On all these CPUs C1, C2 and C4 states can be assigned to each virtual CPU (individual thread). Since Atom features Hyper-Threading technology, each CPU core is recognized as two CPUs by the operating system; so a single-core CPU is recognized as two CPUs or “two threads” using the industry’s jargon. Atom can put any thread into any C1, C2 or C4 states.
Atom can disable a p
ortion of its L2 cache size when entering C4 or C4E states, feature known as “Dynamic Cache Sizing” (Atom 2xx does not support C4 mode and thus doesn’t have this feature). Usually when the CPU enters the C4 state the memory cache is fully turned on, and under C4E state the memory cache is fully turned off.
Another traditional power-saving feature available on Atom CPUs (only in N270 model) is SpeedStep technology. This technology makes the CPU to run at lower clock rates and lower voltages when you are running a program that isn’t demanding the CPU full processing power.[nextpage title=”Chipset”]
Depending on the model, Atom can be paired either with an Intel 945-class chipset (Atom 2xx and N2xx) or with the new Intel US15W (Atom Z5xx), also known as “Intel System Controller Hub” or simply SCH. It is interesting to note that Intel has granted a license to SiS to design chipsets targeted to Atom CPUs, so you may see in the future Atom CPUs using chipsets from this manufacturer.
Since Intel 945 chipsets use two relatively big chips, CPUs using these chipsets are targeted to laptops only, as they can’t fit the small footprint required for smaller applications. In theory any Intel 945 chipset can be used, but Intel recommends the mobile version and you will probably see products with Intel 945GSE, which is the chipset recommended for the “NetBook’08” platform. All memory and I/O features for a small laptop based on Atom CPU will depend on the chipset used.
The new US15W chipset, on the other hand, is a very small single-chip solution, allowing Atom CPUs to be used on handheld devices with internet access. It uses a completely new design and some of its main features are:
- Graphics engine with full hardware-based HD video decoder (supporting H.264, MPEG2, MPEG4, VC1 and WMV9 decoding) and 3D graphics capability, running at 200 MHz (Intel Graphics Media Accelerator 500, which is a DirectX 9.0c/Shader 3.0 engine)
- Support for two displays, one internal to the device and one external. They can work as two independent displays or showing the same image at the same time (cloning). The connection between the chipset and the internal LCD display is done through an LVDS (Low-Voltage Signaling Interface) supporting 18- or 24-bit colors, while the connection between the chipset and the external video monitor is done through a SDVO (Serial Digital Video Out) link; this link can be easily converted to any standard output (VGA, S-Video, DVI, HDMI, etc) through an external chip.
- Supports DDR2-400 or DDR2-533 memories up to 1 GB, single-channel (the foil in Figure 3 shows a wrong maximum memory capacity)
- HD Audio controller with 32-bit resolution and up to 192 kHz sampling rate. The actual audio quality will depend on the audio codec used
- Eight USB 2.0 ports
- Two x1 PCI Express lanes
- One ATA-100 port
- Three SDIO ports
Figure 3: Intel US15W chipset main features.
Figure 4: Intel US15W block diagram.
One very interesting thing to notice is that this chipset does not support SATA ports. This was done on purpose, because according to Intel when they were developing this chipset 1.8” hard disk drives were available only with parallel ATA (PATA) interface, not SATA. They also think that mobile internet devices will use SSD (Solid-State Drives) in the near future, not hard disk drives.
[nextpage title=”The Future: Moorestown Platform”]
As we briefly mentioned, “Moorestown” is the codename for the next version of Centrino Atom, scheduled to reach the market in 2009 or 2010. It will feature a “Lincroft” Atom CPU, a “Langwell” chipset and an “Evans Peak” radio chip. As you can see in Figure 5, Intel will add a video encoder to the Atom CPU codenamed “Lincroft,” plus a solid-state disk (SSD) controller to the chipset codenamed “Langwell” and possible support for 3G cell phone capability on “Evans Peak” radio chip.
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