Inside the AMD Bulldozer Architecture

The L2 Memory Cache

The Bulldozer architecture will have a shared L2 memory cache for each two “cores.” An L3 memory cache will be available, shared between all “cores.” The L2 memory cache will be a 16-way set associative cache, with a 1,024-entry TLB (Translation Look-aside Buffer).

AMD BulldozerFigure 6: The L2 memory cache

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