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Inside the Intel Sandy Bridge Microarchitecture

Sandy Bridge is the name of the new microarchitecture Intel CPUs will be using starting in 2011. Let’s see what is new.

Home » Inside the Intel Sandy Bridge Microarchitecture

The AVX Instruction Set

Contents

  • 1. Intro
  • 2. Enhancements to the CPU Pipeline
  • 3. The AVX Instruction Set
  • 4. The Ring Architecture
  • 5. Next Generation Turbo Boost
  • 6. The Integrated Graphics Engine

A while ago, AMD proposed an SSE5 instruction set. However, Intel decided to create its own implementation of what would be the SSE5 instructions, called AVX (Advanced Vector Extensions).
These instructions use the same SIMD (Single Instruction, Multiple Data) concept introduced with the MMX instruction set and used by the SSE (Streaming SIMD Extensions) instructions. This concept consists in using a single big register to store several small-sized data and then process all data with a single instruction, speeding up processing.
The AVX instruction set adds 12 new instructions and increases the size of the XMM registers from 128 bits to 256 bits.
Detailed information about the new AVX instruction set can be found here (look for the Intel Advanced Vector Extensions Programming Reference).

Continue: The Ring Architecture

CPU Tutorials

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For Performance

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