Intel EM64T Technology Explained
64-Bit Mode Features
Contents
Under IA32E 64-bit mode, the CPU gains a lot of new stuff:
- 64-bit addressing space, i.e., applications can address up to 16 EB (exabytes) of RAM (2^64 bytes); however externally current Celeron D, Pentium 4 and Xeon CPUs supporting EM64T have only 36 address lines, meaning they can “only” access 64 GB of RAM (2^36). Xeon DP CPUs supporting EM64T technology have 40 address lines, meaning they can access up to 1 TB (terabyte) of RAM (2^40). These limitations can be changed in the future, so in the future Intel can release CPUs that can access more RAM memory externally (up to 16 EB).
- Eight additional registers: under 64-bit mode the CPU has a total of 16 64-bit registers. These new registers are named R8 through R15. Interesting enough, Intel has decided to use the same naming convention created by AMD on their 64-bit implementation, i.e., using a letter “R” to indicate a 64-bit register. In Figure 1, you can see how the 64-bit RAX register looks like.
Figure 1: Register scheme on EM64T.
- Eight additional registers for SIMD instructions (MMX, SSE, SSE2, SSE3): the CPU has a total of 16 64-bit MMX registers under 64-bit mode. The XMM registers continue to be 128-bit wide, however the number of XMM registers were doubled from eight to 16. These registers are used by SSE floating point operations.
- All registers and instruction pointers are 64-bit wide. FPU registers continue to be 80-bit wide.
- All 64-bit registers continue to use the same division scheme that allows them to be used for 8-bit operations (see Figure 1). For example, the eight-bit AL register is, in fact, the eight least significant bits from RAX register. This scheme is called “uniform byte-register addressing”.
- Fast interrupt-priorization mechanism.
- A new 64-bit instruction pointer, called RIP, that replaces the 32-bit instruction pointer, called EIP.
- A new instruction pointer relative addressing mode, called RIP-relative addressing.