Inside AMD K10 Architecture

Energy-Saving Features

The majority of new features introduced by the new K10 architecture are targeted to save energy – and thus make the CPU to produce less heat.

Here are these features:

• Independent Dynamic Core Technology allows each CPU core to run at a different clock rate. The voltage of the cores, however, is shared and it will be the voltage required by the core that is running at the higher clock rate.
• CoolCore Technology allows the CPU to automatically turn off parts of the CPU that are not being used. Processors based on Core microarchitecture also have a similar feature (“Advanced Power Gating”).

Figure 6: CoolCore Technology.

• Dual Dynamic Power Management (DDPM), informally known as “split-plane,” this technology allows the CPU and the memory controller (which is embedded inside the CPU) to use different power sources – i.e., voltages. This will allow the memory controller to work at higher clock rates – typically 200 MHz above the standard clock. This technology also allows the CPU to reduce its voltage and keep the memory controller working at full speed, when the CPU enters one of its power-saving modes. When installed on older motherboards that don’t have separated power sources for the CPU and for the memory controller, the CPU will work like K8 processors, i.e., will use the single voltage provided to feed both the CPU and the memory controller.

Figure 7: Dual Dynamic Power Management (DDPM).

Figure 8: Dual Dynamic Power Management (DDPM).

• Desktop CPUs will use HyperTransport 3.0 instead of HyperTransport 1.x (server CPUs will adopt HT3 only in the future). There are two goals here. The more obvious is a higher transfer rate for accessing peripherals, as by using HT3 K10-based CPUs will be able to access the external world up to 10,400 MB/s (K8-based CPUs are capable of transferring data up to 4,000 MB/s) – this is an important 2.6x increase in available bandwidth. But the not-so-obvious advantage is power saving, as HT3 allows the CPU to change the HyperTransport clock rate and width (i.e., number of bits that are transferred per clock cycle) on the fly. For example, if the CPU senses that 10,400 MB/s is too much for what it is doing at the moment, it can decrease the HyperTransport clock rate (and width) to a value more compatible to what it is doing. The lower the clock rate and the number of bits that are transferred per clock cycle, the less electrical power is used. Since HT3 keeps compatibility with HT1, K10-based CPUs can be installed on older motherboards, but their HyperTransport bus will work at a lower clock rate. For a complete discussion on HyperTransport 3.0 please read our The HyperTransport Bus Used by AMD Processors tutorial.

Now let’s talk about the CPUs that will use the new K10 architecture.