Inside AMD64 Architecture

Execution Units

AMD64 architecture has three integer execution units (a.k.a. ALU, Arithmetic and Logic Unit, or IEU, Integer Execution Unit), three address generation units (AGU) and three floating-point units (FPUs). It has one integer unit more than Pentium 4. The maximum instruction dispatch rate is of six instructions per clock cycle, the same amount found on Pentium 4.

As you can see in Figure 15, there are certain FP instructions that can only be processed in a specific FPU. FPAD stands for floating-point addition instructions, like ADDPS (which, by the way, is a SSE instruction), while FMUL stands for floating-point multiplication instructions, like MULPS (which, by the way, is a SSE instruction).

Figure 15: AMD64 execution units.