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Signals in the real world are analog: light, sound, you name it. So, real-world signals must be converted into digital, using a circuit called ADC (Analog-to-Digital Converter), before they can be manipulated by digital equipment. In this tutorial we will give an in-depth explanation about analog-to-digital conversion yet keeping a very easy to follow language.
When you scan a picture with a scanner what the scanner is doing is an analog-to-digital conversion: it is taking the analog information provided by the picture (light) and converting into digital.
When you record your voice or use a VoIP solution on your computer, you are using an analog-to-digital converter to convert your voice, which is analog, into digital information.
Digital information isn’t only restricted to computers. When you talk on the phone, for example, your voice is converted into digital (at the central office switch, if you use an analog line, or at you home, if you use a digital line like ISDN or DSL), since your voice is analog and the communication between the phone switches is done digitally.
When an audio CD is recorded at a studio, once again analog-to-digital is taking place, converting sounds into digital numbers that will be stored on the disc.
Whenever we need the analog signal back, the opposite conversion – digital-to-analog, which is done by a circuit called DAC, Digital-to-Analog Converter – is needed. When you play an audio CD, what the CD player is doing is reading digital information stored on the disc and converting it back to analog so you can hear the music. When you are talking on the phone, a digital-to-analog conversion is also taking place (at the central office switch, if you use an analog line, or at you home, if you use a digital line like ISDN or DSL), so you can hear what the other party is saying.
But, why digital? There are some basic reasons to use digital signals instead of analog, noise being the number one.
Since analog signals can assume any value, noise is interpreted as being part of the original signal. For example, when you listen to a LP record, you hear noise because the needle is analog and thus don’t know the difference from the music originally recorded from the noise inserted by dust or cracks.
Digital systems, on the other hand, can only understand two numbers, zero and one. Anything different from this is discarded. That’s why you won’t hear any unwanted noise when listening to an audio CD, even if you played it thousands of times before (actually depending on your sound system you can hear some noise when playing audio CDs, but this noise, called white noise, isn’t produced by the CD media, but by the CD player, amplifier or cables used, and is introduced in the audio path after the digital data found on the CD was already converted back to analog – as you see, the problem lies in the analog part).
Another advantage of digital system against analog is the data compression capability. Since the digital counterpart of an analog signal is just a bunch of numbers, these numbers can be compressed, just like you would compress a Word file using WinZip to shrink down the file size, for example. The compression can be done to save storage space or bandwidth. On all the examples given so far no compression is used. We will talk again about it when discussing surround sound.
[nextpage title=”How It Works: Sampling”]
For our explanations, consider the analog signal found in Figure 1. Let’s assume that it is an audio signal, since this the most popular applications for analog-to-digital and digital-to-analog conversions. The “y” axis represents voltage while the “x” axis represents time.
What the ADC circuit does is to take samples from the analog signal from time to time. Each sample will be converted into a number, based on its voltage level. In Figure 2 you see an example of some sampling points on our analog signal.
The frequency on which the sampling will occur is called sampling rate. If a sampling rate of 22,050 Hz is used, for example, this means that in one second 22,050 points will be sampled. Thus, the distance of each sampling point will be of 1 / 22,050 second (45.35 µs, in this case). If a sampling rate of 44,100 Hz is used, it means that 44,100 points will be captured per second. In this case the distance of each point will be of 1 / 44,100 second or 22.675 µs. And so on.
During the digital-to-analog conversion, the numbers will be converted again into voltages. If you think about it for a while, you will see that the waveform resulted from the digital-to-analog conversion won’t be perfect, as it won’t have all the points from the original analog signal, just some of them. In other words, the digital-to-analog converter will connect all the points captured by the analog-to-digital converter, any values that existed originally between these points will be suppressed.
You can see an example in Figure 3, where we show how the signal would be after being converted to digital and back to analog. As you can see, the original waveform is more “rounded”.
So, the more sampling points we use – i.e., the higher the sampling rate –, the more perfect will be the analog signal produced by the digital-to-analog converter (DAC). However, the more samples we capture more storage space is necessary to store the resulting digital data. For example, an analog-to-digital conversion using a 44,100 Hz sampling rate will generate twice the number of data as a conversion using a 22,050 Hz sampling rate, as it will capture twice the samples from the original waveform.
If you use a low sampling rate, the waveform generated at the DAC will be very different from the original analog signal. If it is music, for example, the music you will play will have a very bad quality.
So, we have this dilemma: if the sampling rate is too high, the output quality will be close to perfection, but you will need a lot of storage space to hold the generated data (i.e., the generated file will be very big); if the sampling rate is too low, the output quality will be bad.
How can you know the best sampling rate to be used during analog-to-digital conversions to have the best storage/quality balance? The answer is the Nyquist Theorem.
This theorem states that the sampling rate on analog-to-digital conversions must be at least two times the value of the highest frequency you want to capture.
Since the human ear listens to sounds up to the frequency of 20 kHz, for music we need to use a sampling rate of at least 40,000 Hz. In fact, the CD uses a 44,100 Hz sampling rate, thus capturing more than our ears can hear (this value was arbitrated by Phillips and Sony when they created the CD). Some professional audio applications use an even higher sampling rate.
The phone system, on the other hand, was created to transmit only human voice, which has a lower frequency range, up to 4 kHz. So on the digital part of the phone system, an 8,000 Hz sampling rate is used. That’s why if you try to transmit music through the phone the quality is bad: the phone circuitry cancels all frequencies above 4 kHz (ask a friend to put his/her phone near a stereo playing and you will hear what we are talking about).
[nextpage title=”How It Works: Resolution”]
The value of each sampled point will be stored on a fixed-length variable. If this variable uses eight bits, this means it can hold values from 0 to 255 (2^8 = 256). If this variable uses 16 bits, this means it can hold values from 0 to 65,535 (2^16 = 65,536). And so on.
So, if you are using an 8-bit analog-to-digital converter, the lowest value will be zero and the highest value will be 255. If a 16-bit analog-to-digital converter is used, the lowest value will be zero and the highest value will be 65,535. See Figure 4.
What the ADC does is to divide the “y” axis in “n” possible parts between the maximum and the minimum values of the original analog signal, and this “n” is given by the variable size. If the variable size is too small, what will happen is that two sampling points close to each other will have the same digital representation, thus not corresponding exactly to the original value found on the original analog signal, making the analog waveform available at the DAC output to not have the best quality.
Once again, the highest the variable size, the better the quality will be, but more storage space will be needed. Using a 16-bit variable will required twice the storage space if an 8-bit variable was used, but the quality will be far better.
One of the ways to know the necessary number of bits for an ADC is by calculating the desired noise level. Since the values sampled from the original analog signal will several times need to be “rounded” to the nearest possible digital equivalent, this provides what is called quantization noise. The tolerable noise level depends on the application. The phone system can have a higher noise level than an audio CD, for example, since we want to hear our CDs with the best possible quality.
The signal-to-noise ratio (SNR), which measures the noise level, can be easily calculated through this formula, where n is the number of bits used on the ADC:
SNR = 6.02 x n + 1.76 dB
The higher the SNR, the better. An 8-bit ADC provides a SNR of 49.9 dB, while a 16-bit SNR provides a SNR of 98 dB (which is, by the way, a virtually no-noise value).
Audio CDs use 16-bit resolution, while the phone system uses 8-bit resolution. High-end and professional audio applications use 20- or even 24-bit resolution.
In summary, while the sampling rate give us the analog-to-digital “x” axis resolution, the variable size gives us the “y” axis resolution.
Knowing the sampling rate and the variable size (a.k.a. resolution) you can easily calculate the storage space (or the bandwidth, in the case of audio transmission) that will be necessary to store the data generated by the ADC.
The phone system, for example, uses an 8,000 Hz sampling rate and each sample is stored on an eight-bit variable. So the transmission rate of the analog-to-digital conversion is of 64,000 bits per second (8,000 x 8) or 64 Kbps (this is rounded, since 1 K = 1,024; thus 64 Kbps would be 65,536 bps and not 64,000 bps). If you whish to record a phone conversation, the space that it would require would be 8,000 bytes per second (64,000 / 8) or 480,000 bytes per minute (8,000 x 60), i.e., 468.75 KB per minute.
The CD uses a 44,100 Hz sampling rate and each sample is stored on a 16-bit variable. Also, the CD has two independent channels (left and right, what is played at one channel can be completely different from what is played at the other). So the transmission rate of the analog-to-digital conversion of the CD system is of 1,411,200 bps (44,100 x 16 x 2) or 1.41 Mbps (once again this is rounded, since 1 M = 1,048,576). The storage space that is necessary is of 176,400 bytes per second (1,411,200 / 8) or 10,584,000 bytes per minute (176,400 x 60), i.e., 10 MB per minute.
Since each CD can hold up to 74 minutes of music, this means that a CD can store 740 MB of music information (74 minutes x 10 MB per minute). On CD-ROM mode a CD can store less, 650 MB, because part of its storage space is used for error-correction code (ECC).
The “pure” data obtained from the analog-to-digital conversion is better known as PCM, Pulse Code Modulation. PCM is also referred as “uncompressed digital audio”. CDs use PCM audio, as we have been explained so far. DVDs, however, can use PCM audio as an option, but they can also use compressed audio – which is our next subject.
[nextpage title=”Surround Audio: Audio Compression”]
When we made the math to find out how much storage space the CD-quality audio would need, we had to multiply the required storage space per two, since the CD uses two independent audio channels. You can record totally different audio streams on each channel (left and right) of a CD. They are completely independent.
So, imagine how much storage space a surround sound system would need, since they use four or more independent audio channels. If we make the math for the most popular surround sound format nowadays, the 5.1 – which is used by DVDs –, we would come to the conclusion that it would require 441,000 bytes per second of storage space, or 25 MB per minute, if CD-quality audio is used. If you take a typical one and a half hour movie, you would need 2.2 GB of storage space just for storing the audio data, not counting the movie itself!
Just one parenthesis. For the above calculations we considered only five channels of audio. The sixth channel, the subwoofer channel (a.k.a. LFE, Low Frequency Effects), would require less storage space, since we can use a lower sampling rate for it, since it is used only for lower-frequency sounds. That’s why the name is “5.1” and not “6”: the sixth channel isn’t a “full” channel. If we considered the subwoofer channel, the required storage space would be even greater.
The solution is to use audio compression, to cut off the amount of required storage space. All audio compression algorithms available on DVDs are data-loss, i.e., the output signal is not equal to the original sound. Even though experts claim that a regular user wouldn’t notice the difference between uncompressed (PCM) audio and data-loss compressed audio, audiophiles claim that they can hear the difference. That’s why for certain titles 2-channel PCM audio (i.e., CD-quality audio) is an option.
The two most popular commercial audio compression algorithms are Dolby Digital (also known as AC3) and DTS (Digital Theater System). Dolby Digital bitrate varies between 384 Kbps and 448 Kbps, although it is theoretically possible to go as high as 640 Kbps. DTS bitrate varies between 768 Kbps and 1,536 Kbps. Since DTS uses a higher bitrate than AC3, experts claim that it has a better quality than Dolby Digital, since the higher the bitrate, the less original data was lost on the compression. Just to put those numbers in perspective, a 5-channel PCM audio with CD-quality has a bit rate of 3,445 Kbps (once again not counting the LFE channel).
On the practical side, there are other differences. DVDs with DTS-encoded audio can only be played on home theater receivers capable of decompressing DTS, while all home theater receivers can play DVDs with Dolby Digital compressed audio. On movies theaters, Dolby Digital-based movies use an optical audio track with the digital data encoded, while DTS-based movies have just a control track that commands a CD-ROM that has the digital audio information stored.
[nextpage title=”Inside an ADC”]
You can consider the analog-to-digital converter as a closed box, as shown in Figure 5. But what is inside the box? That is exactly what we are going to explain now.
There are several ways to build an ADC. We can divide ADC design into four main groups:
- Parallel design (also known as Flash ADC);
- Digital-to-Analog Converter-based design (e.g., ramp counter, successive approximation, tracking);
- Integrator-based design (e.g., single-slope, dual-slope);
- Sigma-delta design (also known as delta-sigma, 1-bit ADC or oversampling ADC).
Each one of these main groups can have several different implementations. We are going to talk about each one of these groups individually.
[nextpage title=”Parallel Design”]
The Flash ADC, also called parallel ADC, is very easy to understand. It works by comparing the input voltage – i.e., the analog signal – to a reference voltage, which would be the maximum value achieved by the analog signal. For example, if the reference voltage is of 5 volts, this means that the peak of the analog signal would be 5 volts. On an 8-bit ADC when the input signal reached 5 volts we would find a 255 (11111111) value on the ADC output, i.e., the maximum value possible.
Then the voltage reference is lowered through a resistor network and other comparators added, so the input voltage (analog signal) can be compared to other values.
In Figure 6, you can see a 3-bit Flash ADC. The comparison is done through an op amp. All resistors have the same value.
The priority encoder can be done using XOR gates and a series of diodes and resistors, like shown in Figure 7, or a single chip like 74148 (3-line to 8-line priority encoder).
Even though Flash ADC uses a very simple design, it requires a lot of components. The number of required comparers is 2^n-1, where n is the number of output bits. Thus for an eight-bit Flash ADC 255 comparers would be necessary, and for a 16-bit Flash ADC, 65,535!
On the other hand, Flash ADC is the fastest ADC type available. The digital equivalent of the analog signal will be available right away at it output (it will only have the propagation delay inserted by the logic gates) – hence the name “flash”.
Another advantage of Flash ADC is that you can create an ADC with non-linear output. Usually ADCs have a linear output, i.e., each digital number corresponds to a fixed voltage increase on the analog input. For example, on the 3-bit ADC shown above with a Vref of 5 V, each digital number would represent 625 mV (5 V / 2^3). So 0 V = 000, 0.625 V = 001, 1.250 V = 010 and so on up to 5 V = 111.
Since Flash ADC comparisons are set by a set of resistors, one could set different values for the resistors in order to obtain a non-linear output, i.e., one value would represent a different voltage step from the other values.
[nextpage title=”DAC-Based Designs”]
There are a few ways to design an ADC using a DAC as part of its comparison circuit. We will present you two of them: ramp counter and successive approximation.
Ramp Counter ADC
Ramp counter ADC, also called digital ramp ADC, is shown in Figure 8. Vin is the analog input and Dn through D0 are the digital outputs. The control line found on the counter turns on the counter when it is low and stops the counter when it is high.
The basic idea is to increase the counter until the value found on the counter matches the value of the analog signal. When this condition is met, the value on the counter is the digital equivalent of the analog signal.
It requires a START pulse for each analog voltage you want to convert into digital. The END signal represents the end of the conversion for each individual voltage (each sample), and not for the entire analog signal. Each clock pulse moves the counter. Supposing an 8-bit ADC, for converting the analog value for “128” into digital, for example, it would take 128 clock cycles.
It works by counting from 0 to the maximum possible value (2^n-1) until it “finds” the correct digital value for the analog voltage present at Vin. When this is true, the END signal is given and the digital value for Vin is for at Dn through D0.
So the main problem with this circuit is that it is very slow, as it would require up to 2^n-1 clock cycles to convert each sample. For an eight-bit ADC, it would take up to 255 clock cycles to convert a single sample. For a 16-bit ADC it would take up to 65,535 clock cycles to convert one sample.
Successive Approximation ADC
The second classical ADC circuit using DAC design is called successive approximation, which is the most used one, shown in Figure 9. Vin is the analog input and Dn through D0 are the digital outputs. As you can see, it uses a buffer, so the digital data is still available while the converter is processing the next sample. SAR stands for Successive Approximation Register. It has the same control signals as the ramp counter ADC: START, which commands the ADC to start the conversion, CLOCK and END, which tells us that the conversion of that particular sample has finished.
While the ramp counter ADC does the analog-to-digital conversion counting from 0 to the maximum possible value (2^n-1) until it “finds” the correct digital value for Vin, the successive approximation ADC starts first setting the MSB (most significant bit, on an eight-bit ADC it would be D7). In order to facilitate the explanations below, consider an eight-bit ADC.
The comparison between Vin and the DAC output will tell the control unit if this bit should remain set at 1 or should be set at 0, as the op amp will tell right away the control unit if the sample value is greater or lower than 128 (2^7). Then D6 is set to one, and from the comparison done by the op amp, the control unit will know if this bit should remain set or not. And so on.
The good thing about the successive approximation ADC is its speed. At the worst case it will find the correct digital value for the sample at n clock cycles, where n is the number of bits used. For an eight-bit ADC, the digital value for each sample can be found in up to eight clock cycles (compare to 255 on the ramp counter), and for a 16-bit ADC the digital value for each sample can be found in up to 16 clock cycles (compare to 65,535 on the previous circuit).
And, as we mentioned, another great advantage of this circuit is the use of an output buffer, which allows the circuit that is fed by the ADC to read the digital data while the ADC is already working on the next sample.
[nextpage title=”Integrator-Based Designs”]
There are a few ways of designing analog-to-digital converters using an integrator. Let’s take a look at two of them, single-slope ADC and delta-sigma ADC.
In Figure 10, you can see a single-slope ADC. If you pay close attention, you will see that it is very similar to a ramp counter ADC, as it uses a counter, but instead of using a DAC for generating the comparison voltage, it uses a circuit called integrator, which is basically formed by a capacitor, a resistor and an operational amplifier (op amp). The MOSFET transistor makes the necessary control circuit.
The integrator produces a sawtooth waveform on its output, from zero to the maximum possible analog voltage to be sampled, set by -Vref. The minute the waveform is started, the counter starts counting from 0 to 2^n-1, where n is the number of bits implemented by the ADC. When the voltage found at Vin (the analog signal) is equal to the voltage achieved by the triangle waveform generated by the integrator, the control circuit captures the last value produced by the counter (by trigging the output buffer clock pin), which will be the digital correspondent of the analog sample being converted. At the same time, it resets the counter and the integrator, starting the conversion of the next sample.
Like the successive approximation ADC, this circuit uses an output buffer, meaning that the last converted value can be read while the ADC is converting the current value.
Even though its design is simpler than ramp counter design, it is still based on a counter, and thus suffering from the same basic problem found on ramp counter design: speed. It requires up to 2^n-1 clock cycles to convert each sample. For an eight-bit ADC, it would take up to 255 clock cycles to convert a single sample. For a 16-bit ADC it would take up to 65,535 clock cycles to convert one sample.
Another popular design based on this one is called dual-slope ADC, which solves an inherent single-slop problem called calibration drift, which leads to inaccuracy over time because the integrator isn’t linked to the clock signal (i.e., the sawtooth waveform isn’t synchronized with the counter clock).
A classic dual-slope ADC can be seen in Figure 11.
The analog switch first connects Vin to the integrator. With that, the integrator starts generating the sawtooth waveform, and the switch position will remain set at Vin during a fixed number of clock cycles. When this number of clock cycles is reached, the analog switch moves its position to allow –Vref to enter the integrator. Since –Vref is a negative voltage, the sawtooth waveform goes towards zero, using a number of clock cycles proportional of the Vin value.
For a better understanding, see Figure 12, where we show the waveform at the integrator output. So, T1 is fixed, while T2 duration is proportional to the value of Vin. Vin sets the slope angle: the higher Vin is, the higher the angle will be.
T2 = T1 x Vin / Vref.
[nextpage title=”Sigma-Delta ADC”]
The sigma-delta ADC – also called delta-sigma, 1-bit ADC or oversampling ADC – uses a different approach. We can divide it into two major blocks: analog modulator, which takes the analog signal and converts it into a stream of bits, and digital filter, which converts the serial stream from the modulator into an “usable” digital number.
The analog modulator is somewhat similar to a dual-slope ADC, however using a 1-bit DAC as a feedback loop. The basic sigma-delta modulator design can be found in Figure 14.
The analog signal will make the first op amp, which is a summing integrator, to create a sawtooth waveform proportional to the analog signal voltage. This sawtooth waveform found on the integrator output is then compared with zero volts by the second op amp, which is a comparator. It can be considered a 1-bit ADC, since its output will have only two states, high or low, depending whether the integrator output is positive or negative. The comparator output is stored on the D-type flip-flop, which is a one-bit static memory. This flip-flop is clocked at a very high frequency.
Then the flip-flop output is used to feedback the circuit through a one-bit DAC. This one-bit DAC will basically convert the “0” or “1” stored at the flip-flop into a positive or negative reference voltage to be added to the input of the summing integrator.
So the summing integrator will sum the next sample with the result of the previous sample (a positive or a negative voltage), aiming to maintain zero at the integrator output.
The result is that at the flip-flop output we will have a series of zeros and ones that correspond the sampled data: the bitstream average level represents the analog input signal average voltage.
Since the clock rate used at the flip-flop is very high, data is sampled many times over, a technique known as oversampling. The higher the clock, the higher the precision of the sigma-delta ADC.
In real-world applications, the flip-flop clock rate will be 64 times higher than the sampling rate (i.e., a oversampling rate of 64). So, for a 44,100 Hz sampling rate, the flip-flop clock rate will be of 2,822,400 Hz.
Another way to increase the ADC precision and thus reducing noise is to implement a second summing integrator between the original integrator and the comparator. This implementation would be called second order sigma-delta ADC. Commercial hi-end ADCs for audio application can use a fifth order analog modulator.
The problem with sigma-delta ADCs would be that with using just one bit the SNR would be too low. If you remember our formula SNR = 6.02 x n + 1.76 dB, sigma-delta ADCs would have a SNR of only 7.78 dB.
However, due to oversampling, the quantization noise is thrown to the high frequencies of the spectrum, and not spread all over the spectrum as it occurs with other designs. This effect is called shaped noise. With all the noise concentrated in a specific portion of the spectrum – on a frequency range above the sampled data –, is quite easy to construct a filter to remove it, thus improving SNR. This kind of filter is known as low pass filter (which allows only frequencies below a certain trigger frequency to pass through it) and this filtering is done on the digital filtering stage.
The use of this kind of filter improves the SNR in 9 dB for every doubling of the clock rate used (9 dB/octave). Without it SNR improves 3 dB/octave only.
So, a first order sigma-delta ADC with an oversampling rate of 64 (2^6) would have a SNR of 54 dB (9 dB x 6).
If we use the SNR formula again, we will come to the conclusion that the effective number of bits (ENOB) can be calculated using:
ENOB = (SNR – 1.76 dB) / 6.02
This means that a first order sigma-delta ADC with an oversampling rate of 64 has the same performance of a multi-bit ADC with a resolution of 8 bits – but using only one bit!
Increasing the number of summing integrators also improves SNR. The SNR improvement can be calculated by the formula 6 x L + 3 dB, where L is the order number. So a second order sigma-delta ADC provides a SNR of 15 dB/octave, a third order provides a SNR of 21 dB/octave, a fourth order a SNR of 27 dB/octave and a fifth order a SNR of 33 dB/octave.
An easier way to calculate the effective number of bits it through the formula:
ENOB = ((L + 0.5) x n) + 1
Where L is the order number of the sigma-delta ADC and n is the oversampling factor given by 2^n; for a 64x oversampling, n would be 6.
So a second order sigma-delta ADC with a 64x oversampling achieves an effective number of bits of 16 (a 98 dB SNR), thus achieving the same performance of a conventional 16-bit ADC with a simpler (and cheaper) construction.
The next step is to know what digital number the bitstream found at the analog modulator represents, what is done by the digital filtering block, which does also the low pass filtering already explained.
Since the bitstream is oversampled (i.e., its clock is higher than the sampling rate), this stage also “reduces” its clock rate to the sampling rate. This process is known as decimation.
[nextpage title=”ADC On the PC”]
The most logical place you will find an ADC on a PC is on the sound card. Whenever you use a mike – for recording your own voice or for talking with friends using VoIP programs like Skype – or the line in input for transforming audio produced by other equipment (like your tape deck) into Wav or even MP3 files, you are in fact using your sound card’s analog-to-digital converter.
Nowadays all PCs have a sound card embedded on the motherboard – even if you won’t use it. This is because the motherboard chipset – more specifically, the south bridge chip – has an audio interface. The ADC (for recording audio) and DAC (for reproducing audio), however, isn’t integrated in the south bridge, but on a separated chip called codec (coder/decoder).
Of course if you use an add-on sound card you will be using the ADC and the DAC provided by the sound card and not by the codec chip. Also, some motherboards instead of using the audio capability of the chipset provide an extra complete audio chip, which has its own ADC and DAC. For a more detailed discussion about on-board audio options, we suggest you to read our tutorials “How Does On-Board Audio Work” and “Understand On-Board Audio Features”.
What we wish to show you is how a codec works. For this, take a look at Figure 16, where we present the block diagram of Analog Devices AD1888A codec. What can you learn by just looking at this diagram? Can you find the ADC?
In Figure 16 you can easily see all inputs connected to the 16-bit ADC through a mixer. One question you might have is where the 16 data outputs are located – after all, this codec uses a 16-bit ADC. As we mentioned, the codec is connected to the chipset (south bridge chip). The communication of these two chips is done using a serial interface, not parallel – i.e., the codec transmits each bit one by one to the chipset. So there are just two data wires connecting them (one input, SDATA_IN, and one output, SDATA_OUT). The AC’97 interface unit is the responsible for such interface.
Analyzing Figure 16 you will also discover that AD1888A has six individuals 20-bit DACs – one for each channel, so it provides six-channel audio – and it has a digital audio (SPDIF) output, and several other features, like EAPD (External Amplifier Power Down), which can disable an external amplifier if no audio is being produced, and jack sense (JS pins) which can automatically reconfigure the jacks located on the motherboard depending on what kind of device you plugged on them.