Everything You Need to Know About The QuickPath Interconnect (QPI)

Introduction

Since the beginning of times Intel CPUs use an external bus called Front Side Bus or simply FSB that is shared between memory and I/O requests. The next generation of Intel CPUs will have an embedded memory controller and thus will provide two external busses: a memory bus for connecting the CPU to the memory and an I/O bus to connect the CPU to the external world. This bus is a new bus called QuickPath Interconnect (QPI) and in this tutorial we will be explaining how it works.

On Figures 1 and 2 we are comparing the traditional architecture used by Intel CPUs and the new architecture that will be used by Intel CPUs with an integrated memory controller.

Figure 1: Architecture used by current Intel CPUs.

Figure 2: Architecture used by Intel CPUs with embedded memory controller.

This is exactly the same idea that AMD has been using since 2003, when they released their first Athlon 64 CPU. Currently all CPUs from AMD have an integrated memory controller and they use a bus called HyperTransport to make the I/O communications. Though QuickPath Interconnect and HyperTransport have the same goal and work in a very similar fashion, they are not compatible.

By the way, technically speaking both QuickPath Interconnect and HyperTransport aren’t busses but a point-to-point connection. A bus is a set of wires that allows several components to be connected to it at the same time, while a point-to-point connection is a path connecting only two devices. Even though it is technically wrong call these connections “busses,” we will keep calling them this way for simplicity and also to facilitate the comprehension of the text by laymen that call these connections this way.

We will now explain you how the QuickPath Interconnect works. If you are interested you can read our tutorial The HyperTransport Bus Used By AMD Processors to compare these two external busses.