We are a participant in the Amazon Services LLC Associates Program, an affiliate advertising program designed to provide a means for us to earn fees by linking to Amazon.com and affiliated sites.

Intel has very high-end research and development facilities – including development sites for several Intel CPUs – and chip factory in Israel, so we were pretty excited in traveling half the Globe just to attend the first IDF held in Tel Aviv. We expected to see more info on forthcoming Intel products and we hit bull’s eye: we could learn a lot more about new Intel CPUs, especially the new Merom/Conroe/Woodcrest family, the new Monahans cell phone application CPU and a little bit about the forthcoming 45 nm technology, since all these technologies are being developed in Israel.

At this IDF we could see a Conroe CPU prototype – which is the codename of the desktop CPU using Pentium M architecture that will replace Pentium 4 – and also an OEM notebook from ASUS based on the forthcoming Yonah CPU, which is the dual-core Pentium M manufactured on the 65 nm process.

Figure 1: Conroe CPU prototype.

Figure 2: ASUS OEM notebook based on Yonah CPU.

We had the chance of sitting and talking to Ron Friedman, Intel’s VP in charge of Intel’s MMG (Mobility Microprocessor Group) team, based in Haifa and which develops all Pentium M-class CPUs (Banias, Dothan, Yonah, Meron and even the next-generation 45 nm Intel CPU) and also the microarchitecture that will be used on desktop and servers starting next year.

The first successful commercial product from the Haifa team was Pentium with MMX technology (codenamed P55C, remember that one?) back in 1996. The next CPU development from them was a project codenamed Timna, a highly integrated CPU for the low-end market, which was cancelled when the product was finished and ready to go into production, basically because Intel decided to use the expensive Rambus memory with it.

From the Timna experience, however, came the expertise in projecting CPUs with great performance/power ratio, so they decided to go ahead with the project of a relatively low power CPU that would, at the same time, provide a great performance at lower clock frequency compared to desktop CPUs, codenamed Banias. This was 1999 and they didn’t have a clue what the market response would be, especially because at the time everybody was only trying to reach higher clock frequencies, without caring too much with consumption or heat dissipation. This CPU was released in 2003 as Pentium M and in fact it was so successful that Intel decided to use its microarchitecture on all next-generation CPUs, from mobile to server, which we are going to be talking more in the next page.

Friedman explained us that this decision had a lot to do with multi-core technology. For example, making a dual-core version of Pentium 4 “Prescott”, which can easily go around 100 W, is a pain, because theoretically its dual-core version would dissipate around 200 W. Even if the CPU dissipated 60 W making it double core would be very hard.

With Yonah, the dual-core Pentium M CPU manufactured in the new 65 nm process, ready to be released on the beginning of 2006, the Haifa team is now working on the 45 nm manufacturing process. Why shrinking down to 45 nm? According to Friedman, there are three basic reasons:

• Cost: With a smaller silicon die, Intel can have more CPUs from the wafer where the CPUs come from.
• Bigger cache: The big issue for memory cache is its size. On several CPUs the L2 cache is actually bigger than the CPU itself. So, reducing the size of the die it is possible to create a bigger L2 cache without increasing the size of the chip.
• Speed and frequency: A smaller die has its circuits closer, making it faster for them to communicate to each other.

The problem, however, is current leakage. Transistors have an inherent leakage problem. When transistors are turned off, they are not exactly turned off; they let a little bit of electrical current to flow. On old CPUs operating at high voltages this wasn’t a problem, because the leaked current would be negligible. On modern CPUs, however, not only the leaked current can be misinterpreted as if the transistor is turned on when in fact it is turned off, but also the leaked current is consuming energy, thus increasing the CPU power dissipation. So leakage is one of the enemies of lowering the CPU power consumption and heat dissipation.

[nextpage title=”Intel’s Next Generation Microarchitecture”]

On this IDF we could get more details on the next microarchitecture that will be used on all new Intel CPUs starting on the second half of 2006 and which was developed by the Haifa team. As we mentioned, this microarchitecture is based on Pentium M’s and not on Pentium 4’s. We have already posted a tutorial about Pentium 4 microarchitecture, so you may be interested in reading it for better understanding this subject and also for understanding the technical terms we are talking about below. This will be Intel’s 8th x86 microarchitecture generation.

First, it will use a 14-stage pipeline, opposed to Pentium 4’s 21-stage pipeline and to Prescott’s 30-stage pipeline. So in this respect this new microarchitecture is more like Intel’s 6th generation CPUs, like Pentium III, than Intel’s 7th generation CPUs.

It will have four dispatch units against the three used on Pentium 4. Simply put, it will be able to send more microinstructions per time to the CPU execution units, which obviously increases performance.

On the cache side, it will use a shared L2 cache for all the CPU cores, just like Yonah, the dual-core Pentium M CPU manufactured in the new 65-nm process that will be released in the beginning of next year. This was made in order to decrease the cache-miss rate, i.e., decrease the number of times that the CPU run out of cache and needs to go to the slow RAM memory to grab data. With a shared L2 cache between all CPU cores, the CPU can dynamically give more or less L2 cache for each core depending on the demand. In a dual-core CPU with separated L2 caches, if one core runs out of cache, it must go and get data directly on the RAM memory, even if the L2 cache from the other core has plenty of space available. On the shared model, if the CPU has 2 MB total L2 cache, for example, one core may be using 1.5 MB and the other 0.5 MB of it, thus decreasing the number of times the CPU needs to grab data directly on RAM memory, increasing performance.

Intel is also promising that the L1 memory caches from each core will be able to directly communicate to each other and also a higher bandwidth between the CPU core and the L2 memory cache.

Another thing new on this architecture will be a new multimedia instruction set (SSE4?), the fifth multimedia instruction set since MMX was released back in 1996.

All CPUs will incorporate the 64-bit addressing extension, EM64T.

The difference between Merom, for mobile market, Conroe, for desktops, and Woodcrest, for servers, will be basically the L2 memory cache size, the TLB (Translation Look-aside Buffer) size and the amount of RAM memory the CPU can address. TLB is a table used by the virtual memory system (a.k.a. swap file) that lists the physical address page number associated with each virtual address page number.

[nextpage title=”Monahans Cell Phone Application CPU”]

During this IDF Intel showed their next generation cell phone application CPU, codenamed Monahans. The prototype shown was running at an impressive 1,248 MHz clock rate. It is really amazing to think that a cell phone will be using a CPU clocked higher than desktop CPUs not so long ago.

Figure 3: Monahans cell phone CPU running at 1,248 MHz.

Figure 4: Monahans development board.

So, who needs a cell phone with a CPU running over 1 GHz? The only application that demands such performance level is video. So this is an application CPU targeted to high-end cell phones with big color displays, being able to play videos at 30 FPS (Frames Per Second) instead of 15 FPS, which the current rate for today’s high-end cell phones.

[nextpage title=”IAMT Demo”]

Intel demonstrated their Active Management Technology, IAMT. With this technology it is possible for system administrators to perform the maintenance of the computers remotely, including turning them on, running anything needed, and then turning them off. This maintenance can be even entering the BIOS setup, as it was demonstrated.

So, with this technology administrators can save a lot of time because they don’t need to physically go to where the faulty computer is located.

Also, with Intel’s virtualization technology, which allows the same computer to be divided into several different partitions as if it were several computers, this remote maintenance can be done even with the computer being used by the user while he is doing something else.

Figure 5: Video monitor of the computer being remotely controlled.

Figure 6: Video monitor of the system administrator computer, as you can see it is controlling the BIOS setup of the computer in Figure 5.